1. Field of the Invention
The present invention relates generally to an electrical circuit arrangement for data transfer between registers.
2. Description of the Related Art
In the development of synchronous circuits, what are referred to as combinatorial blocks KBL (also called combinatorial circuits, see FIGS. 1 and 2) always lie between registers (called, for example, an input register RG1 and an output register RG2 below). In order to adhere to the physically conditioned setup and hold times, there are currently three principles for arranging combinatorial blocks and registers:
The running time/delay time KBL-VZ of changes in the signal value by the combinatorial blocks KBL is smaller than the clock period minus the setup time setup/hold-VZ and minus the signal running time RG-VA through a register RG. This is shown in FIG. 1. A combinatorial block KBL is connected between an input register RG1 and output register RG2. The registers RG1 and RG2 are driven with a clock signal T. PA1 The running time of value changes through the combinatorial blocks KBL is greater by a factor N than a clock period of the clock signal T. However, the result is only taken N clock signals later at the output of the output register RG2 after the combinatorial blocks KBL. PA1 The running time of value changes through the combinatorial blocks KBL is greater by a factor N than a clock period of the clock signal T. However, the result is only written into the output register RG2 following the combinatorial blocks KBL N clock signals later. To that end, an enable terminal EN at the output register RG2 is driven with a pulse that is delayed by N clock signals and is generated by a control circuit CON. This may be seen in FIG. 2.
The running time of a combinatorial circuit KBL is designed to the effect that the last possible signal value changes at their outputs always determine the running time. It is thereby assumed that these instances also always occur during operation.
When, however, certain input signals of a combinatorial circuit do not change, then their effect on the running time need not be taken into consideration. When the input signals are input signals that determine the running time of a combinatorial circuit, then the running time through the combinatorial circuit is shortened in this case.
German Letters Patent DE 36 06 406 C2 discloses a circuit arrangement with combinatorial blocks wherein the output signals thereof are output at output registers connected following the combinatorial blocks.
Further, European Patent Application EP 04 56 399 A2 discloses a circuit with combinatorial blocks and memory units.